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rev. a adg3241 2.5 v/3.3 v, 1-bit, 2-port level translator bus switch in sot-66 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. features 225 ps propagation delay through the switch 4.5 switch connection between ports data rate 1.5 gbps 2.5 v/3.3 v supply operation selectable level shifting/translation level translation 3.3 v to 2.5 v 3.3 v to 1.8 v 2.5 v to 1.8 v small signal bandwidth 770 mhz tiny 6-lead sc70 package and 6-lead sot-66 package applications 3.3 v to 1.8 v voltage translation 3.3 v to 2.5 v voltage translation 2.5 v to 1.8 v voltage translation bus switching bus isolation hot swap hot plug analog switch applications functional block diagram be a b general description the adg3241 is a 2.5 v or 3.3 v, single digital switch. it is designed on a low voltage cmos process, which provides low power dissipation yet gives high switching speed and very low on resistance. this allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. the switch is enabled by means of the bus enable ( be ) input signal. this digital switch allows a bidirectional signal to be switched when on. in the off condition, signal levels up to the supplies are blocked. this device is ideal for applications requiring level translation. when operated from a 3.3 v supply, level translation from 3.3 v inputs to 2.5 v outputs is allowed. similarly, if the device is operated from a 2.5 v supply and 2.5 v inputs are applied, the device will translate the outputs to 1.8 v. in addition to this, a level translating select pin ( sel ) is included. when sel is low, v cc is reduced internally, allowing for level translation between 3.3 v inputs and 1.8 v outputs. this makes the device suited to applications requiring level translation between different supplies, such as converter to dsp/microcontroller interfacing. product highlights 1. 3.3 v or 2.5 v supply operation. 2. extremely low propagation delay through switch. 3. 4.5 ? switches connect inputs to outputs. 4. level/voltage translation. 5. tiny sc70 package and sot-66 package.
rev. a e2e adg3241especifications 1 b version parameter symbol conditions min typ 2 max unit dc electrical characteristics input high voltage v inh v cc = 2.7 v to 3.6 v 2.0 v v inh v cc = 2.3 v to 2.7 v 1.7 v input low voltage v inl v cc = 2.7 v to 3.6 v 0.8 v v inl v cc = 2.3 v to 2.7 v 0.7 v input leakage current i i 0.01 1 a off state leakage current i oz 0 a, b v cc 0.01 1 a on state leakage current 0 a, b v cc 0.01 1 a maximum pass voltage v p v a /v b = v cc = sel = 3.3 v, i o = e5 a 2.2 2.5 2.7 v v a /v b = v cc = sel = 2.5 v, i o = e5 a 1.5 1.8 2.1 v v a /v b = v cc = 3.3 v, sel = 0 v, i o = e5 a 1.5 1.8 2.1 v capacitance 3 a port off capacitance c a off f = 1 mhz 3.5 pf b port off capacitance c b off f = 1 mhz 3.5 pf a, b port on capacitance c a , c b on f = 1 mhz 7 pf control input capacitance c in f = 1 mhz 4 pf switching characteristics 3 propagation delay a to b or b to a, t pd 4 t phl , t plh c l = 50 pf, v cc = sel = 3 v 0.225 ns bus enable time be to a or b 5 t pzh , t pzl v cc = 3.0 v to 3.6 v; sel = v cc 1 3.2 4.6 ns bus disable time be to a or b 5 t phz , t plz v cc = 3.0 v to 3.6 v; sel = v cc 13 4 ns bus enable time be to a or b 5 t pzh , t pzl v cc = 3.0 v to 3.6 v; sel = 0 v 1 3 4 ns bus disable time be to a or b 5 t phz , t plz v cc = 3.0 v to 3.6 v; sel = 0 v 1 2.5 3.8 ns bus enable time be to a or b 5 t pzh , t pzl v cc = 2.3 v to 2.7 v; sel = v cc 13 4 ns bus disable time be to a or b 5 t phz , t plz v cc = 2.3 v to 2.7 v; sel = v cc 1 2.5 3.4 ns maximum data rate v cc = sel = 3.3 v; v a /v b = 2 v 1.5 gbps channel jitter v cc = sel = 3.3 v; v a /v b = 2 v 45 ps p-p digital switch on resistance r on v cc = 3 v, sel = v cc , v a = 0 v, i ba = 8 ma 4.5 8 v cc = 3 v, sel = v cc , v a = 1.7 v, i ba = 8 ma 12 28 v cc = 2.3 v, sel = v cc , v a = 0 v, i ba = 8 ma 5 9 v cc = 2.3 v, sel = v cc , v a = 1 v, i ba = 8 ma 9 18 v cc = 3 v, sel = 0 v, v a = 0 v, i ba = 8 ma 5 8 v cc = 3 v, sel = 0 v, v a = 1 v, i ba = 8 ma 12 power requirements v cc 2.3 3.6 v quiescent power supply current i cc digital inputs = 0 v or v cc ; sel = v cc 0.01 1 a digital inputs = 0 v or v cc ; sel = 0 v 0.1 0.2 ma increase in i cc per input 6 i cc v cc = 3.6 v, be = 3.0 v; sel = v cc 0.15 8 a notes 1 temperature range is as follows: b version: e40 c to +85 c. 2 typical values are at 25 c, unless otherwise stated. 3 guaranteed by design, not subject to production test. 4 the digital switch contributes no propagation delay other than the rc delay of the typical r on of the switch and the load capacitance when driven by an ideal voltage source. since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propag ation delay to the system. propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its inte raction with the load on the driven side. 5 see timing measurement information section. 6 this current applies to the control pin be only. the a and b ports contribute no significant ac or dc currents as they transition. specifications subject to change without notice. (v cc = 2.3 v to 3.6 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted.)
rev. a adg3241 e3e absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v cc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . e0.5 v to +4.6 v digital inputs to gnd . . . . . . . . . . . . . . . . . e0.5 v to +4.6 v dc input voltage . . . . . . . . . . . . . . . . . . . . . e0.5 v to +4.6 v dc output current . . . . . . . . . . . . . . . . . 25 ma per channel operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c sc70 package ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 332 c/w sot-66 package ja thermal impedance . . . . . . . . . 191 c/w (4-layer board) lead temperature, soldering (10 sec) . . . . . . . . . . . . . 300 c ir reflow, peak temperature (<20 sec) . . . . . . . . . . . . 235 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg3241 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table i. truth table be sel ll bls l bls sel
rev. a e4e adg3241 terminology v cc positive power supply voltage. gnd ground (0 v) reference. v inh minimum input voltage for logic 1. v inl maximum input voltage for logic 0. i i input leakage current at the control inputs. i oz off state leakage current. it is the maximum leakage current at the switch pin in the off state. i ol on state leakage current. it is the maximum leakage current at the switch pin in the on state. v p maximum pass voltage. the m aximum pass voltage relates to the clamped output voltage of an nmos device when the switch input voltage is equal to the supply voltage. r on ohmic resistance offered by a switch in the on state. it is measured at a given voltage by forcing a specified amount of current through the switch. c x off off switch capacitance. c x on on switch capacitance. c in control input capacitance. this consists of be and sel . i cc quiescent power supply current. this current represents the leakage current between the v cc and ground pins. it is measured when all control inputs are at a logic high or low level and the switches are off. i cc extra power supply current component for the be control input when the input is not driven at the supplies. t plh , t phl data propagation delay through the switch in the on state. propagation delay is related to the rc time constant r on c l , where c l is the load capacitance. t pzh , t pzl bus enable times. these are the times taken to cross the v t voltage at the switch output when the switch turns on in response to the control signal, be . t phz , t plz bus disable times. this is the time taken to place the switch in the high impedance off state in response to the control signal. it is measured as the time taken for the output voltage to change by v from the original quiescent level, with reference to the logic level transition at the control input. (refer to figure 3 for enable and disable times.) max data rate maximum rate at which data can be passed through the switch. channel jitter peak-to-peak value of the sum of the deterministic and random jitter of the switch channel. pin configuration 6-lead sc70 1 gnd a v cc b be sel adg3241 top view (not to scale) 2 3 6 5 4 6-lead sot-66 1 sel a b gnd v cc be adg3241 top view (not to scale) 2 3 6 5 4 table ii. pin function descriptions pin no. sc70 sot-66 mnemonic description 16 be bus enable (active low) 24 gnd ground reference 33 a port a, input or output 45 b port b, input or output 51 v cc positive power supply voltage 62 sel level translation select ordering guide temperature package model range description package branding adg3241bks-reel e40 c to +85 ct hin shrink small outline transistor package (sc70) ks-6 ska adg3241bks-reel7 e40 c to +85 ct hin shrink small outline transistor package (sc70) ks-6 ska ADG3241BKS-500RL7 e40 c to +85 ct hin shrink small outline transistor package (sc70) ks-6 ska adg3241bry-reel7 e40 c to +85 cs mall outline transistor package (sot-66) ry-6-1 00
rev. a t ypical performance characteristicseadg3241 e5e v a /v b (v ) r on ( ) 0 0 0.5 t a = 25 c sel = v cc 5 10 15 20 25 30 35 40 1.5 2.5 3.5 v cc = 3v v cc = 3.3v v cc = 3.6v 3.0 2.0 1.0 tpc 1. on resistance vs. input voltage v a /v b (v) r on ( ) 0 0 0.5 5 10 15 20 1.5 2.0 1.0 25 c 85 c 40 c = 3.3v sel = v cc v cc tpc 4. on resistance vs. input voltage for different temperatures v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 v cc = 2.7v v cc = 2.5v v cc = 2.3v t a = 25 c sel = v cc i o = e5 a 2.0 1.0 1.0 2.0 3.0 tpc 7. pass voltage vs. v cc v a /v b (v ) r on ( ) 0 0 0.5 5 10 15 20 25 30 35 40 1.5 2.5 v cc = 2.3v v cc = 2.5v v cc = 2.7v t a = 25 c sel = v cc 3.0 2.0 1.0 tpc 2. on resistance vs. input voltage v a /v b (v) r on ( ) 0 0 0.5 5 10 15 85 c 25 c 1.0 40 c = 2.5v sel = v cc v cc 1.2 tpc 5. on resistance vs. input voltage for different temperatures v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 v cc = 3.6v v cc = 3.3v v cc = 3v 3.5 t a = 25 c sel = 0v i o = e5 a 2.0 1.0 1.0 2.0 3.0 tpc 8. pass voltage vs. v cc v a /v b (v ) r on ( ) 0 0 0.5 5 10 15 20 25 30 35 40 1.5 2.5 v cc = 3v v cc = 3.3v v cc = 3.6v 3.5 t a = 25 c sel = 0v 1.0 2.0 3.0 tpc 3. on resistance vs. input voltage v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 3.5 v cc = 3.6v v cc = 3.3v v cc = 3v 3.0 2.0 1.0 1.0 2.0 3.0 t a = 25 c sel = v cc i o = e5 a tpc 6. pass voltage vs. v cc 500 0510 15 20 25 30 35 40 45 enable frequency (mhz) i cc ( a) 50 50 100 150 200 250 300 350 400 450 0 t a = 25 c v cc = 3.3v sel = 0v v cc = sel = 3.3v v cc = sel = 2.5v tpc 9. i cc vs. enable frequency
rev. a e6e adg3241 i o (a) v out (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 0.02 0.04 0.06 0.08 0.10 0 v cc = 3.3v; sel = 0v v cc = sel = 3.3v v cc = sel = 2.5v t a = 25 c v a = 0v be = 0 tpc 10. output low characteristic 2 0 1 e2 e1 e4 e3 0.03 0.1 1.0 frequency (mhz) attenuation (db) 10 1000 100 e6 e7 e5 e8 t a = 25 c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer: r l = r s = 50 tpc 13. bandwidth vs. frequency 4.0 3.5 3.0 e40 e20 0 temperature ( c) time (ns) 20 80 60 40 2.5 2.0 1.5 1.0 0.5 0 v cc = sel = 2.5v enable disable tpc 16. enable/disable time vs. temperature i o (a) v out (v) 0 e0.10 0.5 1.0 1.5 2.0 2.5 3.0 t a = 25 c v a = v cc be = 0 v cc = sel = 2.5v v cc = 3.3v; sel = 0v v cc = sel = 3.3v e0.08 e0.06 e0.04 e0.02 0 tpc 11. output high characteristic frequency (mhz) a ttenuation (db) 0.1 1000 110 e90 0 t a = 25 c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer : r l = r s = 50 e100 e80 e70 e60 e50 e40 e30 e20 e10 100 tpc 14. off isolation vs. frequency data rate (gbps) jitter (ps p-p) 0.5 60 70 80 90 100 50 40 30 20 10 0 v cc = sel = 3.3v v in = 1.5v p-p 20db attenuation 0.7 0.9 1.1 1.3 1.5 1.7 1.9 tpc 17. jitter vs. data rate; prbs 31 0 e0.2 e0.4 0 0.5 1.0 v a /v b (v) q inj (pc) 1.5 3.0 2.5 2.0 e0.6 e0.8 e1.0 e1.2 v cc = 3.3v v cc = 2.5v t a = 25 c sel = v cc on off c l = 1nf tpc 12. charge injection vs. source voltage 4.0 3.5 3.0 e40 e20 0 temperature ( c) time (ns) 20 80 60 40 2.5 2.0 1.5 1.0 0.5 0 v cc = sel = 3.3v enable disable enable disable v cc = 3.3v, sel = 0v tpc 15. enable/disable time vs. temperature data rate (gbps) eye width (%) 0.5 60 70 80 85 90 95 100 75 65 55 50 1.5 1.3 1.1 0.9 0.7 1.7 1.9 v cc = sel = 3.3v v in = 1.5v p-p 20db attenuation % eye width = ((clock period e jitter p-p)/clock period) 100% tpc 18. eye width vs. data rate; prbs 31
rev. a adg3241 e7e v cc = 3.3v sel = 3.3v v in = 1.5v p-p 20db a ttenuation t a = 25 c 50mv/div 200ps/div tpc 19. eye pattern; 1.5 gbps, v cc = 3.3 v, prbs 31 20mv/div 200ps/div v cc = 2.5v sel = 2.5v v in = 1.5v p-p 20db a ttenuation t a = 25 c tpc 20. eye pattern; 1.244 gbps, v cc = 2.5 v, prbs 31
rev. a e8e adg3241 for the following load circuit and waveforms, the notation that is used is v in and v out where vv and v v or v v and v v in a out b in b out a ==== control input be 0v t plh v out v t v ih v h v t v l t plh figure 2. propagation delay v cc v in v out c l r l r l sw1 gnd 2 v cc r t dut pulse generator notes pulse generator for all pulses: t r 2.5ns, t f 2.5ns, frequency 10mhz. c l includes board, stray, and load capacitances. r t is the termination resistor, should be equal to z out of the pulse generator. figure 1. load circuit test conditions symbol v cc = 3.3 v 0.3 v ( sel sel sel l 300 150 150 mv c l 50 30 30 pf v t 1.5 0.9 0.9 v timing measurement information enable disable control input be v in = 0v v in = v cc v out sw1 @ 2v cc v out sw1 @ gnd t plz t pzh t phz t pzl v t 0v v cc v t v h v h ev v l v l + v v cc 0v v t v inh 0v figure 3. enable and disable times table iii. switch position test s1 t plz , t pzl 2 v cc t phz , t pzh gnd
rev. a adg3241 e9e bus switch applications mixed voltage operation, level translation bus switches can provide an ideal solution for inter facing between mixed voltage systems. the adg3241 is suitable for applications where voltage translation from 3.3 v technology to a lower voltage technology is needed. this device can translate from 3.3 v to 1.8 v, from 2.5 v to 1.8 v, or bidirectionally from 3.3 v directly to 2.5 v. figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3.3 v adc and a 2.5 v microprocessor. the microprocessor may not have 3.3 v toler- ant inputs, therefore placing the adg3241 between the two devices allows the devices to communicate easily. the bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 3.3v adc 2.5v 3.3v 2.5v microprocessor adg3241 3.3v figure 4. level translation between a 3.3 v adc and a 2.5 v microprocessor 3.3 v to 2.5 v translation when v cc is 3.3 v ( sel = 3.3 v) and the input signal range is 0 v to v cc , the maximum output signal will be clamped to within a voltage threshold below the v cc supply. adg3241 2.5v 2.5v 3.3v 2.5v 3.3v figure 5. 3.3 v to 2.5 v voltage translation, sel s s sl sel sel 2.5 v to 1.8 v translation when v cc is 2.5 v ( sel = 2.5 v) and the input signal range is 0 v to v cc , the maximum output signal will, as before, be clamped to within a voltage threshold below the v cc supply. in this case, the output will be limited to approximately 1.8 v, as shown in figure 8. adg3241 1.8v 2.5v 2.5v figure 7. 2.5 v to 1.8 v voltage translation, sel s s sl sel sel 3.3 v to 1.8 v translation the adg3241 offers the option of interfacing between a 3.3 v device and a 1.8 v device. this is possible through use of the sel pin. the sel pin is an active low control pin. sel acti- vates internal circuitry in the adg3241 that allows voltage translation betw een 3.3 v devices and 1.8 v devices. adg3241 1.8v 3.3v 3.3v figure 9. 3.3 v to 1.8 v voltage translation, sel sel l sel s s sl sel sel
rev. a e10e adg3241 bus isolation a common requirement of bus architectures is low capacitance loading of the bus. such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications. because the adg3241 is designed specifically for applications that do not need drive yet require simple logic functions, it solves this requirement. the device isolates access to the bus, thus minimizing capacitance loading. b us/ b ackplane l oad a l oad c l oad b l oad d b us switch l ocation figure 11. location of bus switched in a bus isolation application hot plug and hot swap isolation the adg3241 is suitable for hot swap and hot plug applica tions. the output signal of the adg3241 is limited to a voltage that is below the v cc supply, as shown in figures 6, 8, and 10. there fore the switch acts like a buffer to take the impact from hot insertion, protecting vital and expensive chipsets from dam age. in hot plug applications, the system cannot be shut down when new hardware is being added. to overcome this, a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors. the bus switch is turned off during hot plug. figure 12 shows a typical example of this type of application. plug-in card (1) card i/o card i/o ram cpu plug-in card (2) adg3241 adg3241 figure 12. adg3241 in a hot plug application there are many systems, such as docking stations, pci boards for servers, and line cards for telecommunications switches, that require the ability to handle hot swapping. if the bus can be isolated prior to insertion or removal, there is more control over the hot swap event. this isolation can be achieved using bus switches. the bus switches are positioned on the hot swap card between the connector and the devices. during hot swap, the ground pin of the hot swap card must connect to the ground pin of the backplane before any other signal or power pins. analog switching bus switches can be used in many analog switching applications, for example, video graphics. bus switches can have lower on resistance, smaller on and off channel capacitance, and thus improved frequency performance than their analog counterparts. the bus switch channel itself, consisting solely of an nmos switch, limits the operating voltage (see tpc 1 for a typical plot), but in many cases, this does not present an issue. high impedance during power-up/power-down to ensure the high impedance state during power-up or power- down, be should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current- sinking capability of the driver.
rev. a adg3241 e11e 6-lead thin shrink small outline transistor package [sc70] (ks-6) dimensions shown in millimeters 0.22 0.08 0.46 0.36 0.26 8 4 0 0.30 0.15 1.00 0.90 0.70 seating plane 1.10 max 3 5 4 2 6 1 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 1.30 bsc 0.10 max 0.10 coplanarity compliant to jedec standards mo-203ab outline dimensions 6-lead small outline transistor package [sot-66] (ry-6-1) dimensions shown in millimeters seating plane 0.60 0.57 0.53 12 max top view 0.34 max 0.27 nom 0.18 0.17 0.13 bottom view 1.70 1.66 1.50 pin 1 1.30 1.20 1.10 1.70 1.65 1.50 1 3 5 6 2 4 0.10 nom 0.05 min 0.20 min 0.50 bsc 0.25 max 0.17 min 0.30 0.23 0.10 0.26 0.19 0.11
rev. a c04221e0e11/04(a) e12e adg3241 revision history location page 10/04?data sheet changed from rev. 0 to rev. a. changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to product highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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